The subject matter in this application is related to material in two other U.S. patent applications of Roy and Miller, entitled DISTRIBUTED INTERFACE FOR PARALLEL TESTING OF MULTIPLE DEVICES USING A SINGLE TESTER CHANNEL, having Ser. No. 09/260,463, and EFFICIENT PARALLEL TESTING OF INTEGRATED CIRCUIT DEVICES USING A KNOWN GOOD DEVICE TO GENERATE EXPECTED RESPONSES, having Ser. No. 09/260,460, filed on the same date as this application and expressly incorporated herein by reference.
This invention is related to the testing of integrated circuit devices using a semiconductor tester, and more particularly to testing a number of devices in parallel using a single channel of the tester for greater efficiency and throughput.
Integrated circuit (IC) devices are an important part of almost every modern electronic or computer system. To reduce the manufacturing cost of such systems, the manufacturer expects each constituent IC device to be free of defects and to perform according to its specifications. Thus, it is not unusual to expect that every IC device is subjected to rigorous testing prior to being shipped to the system manufacturer.
It has been determined, however, that a significant portion of the total cost of producing an IC device can be attributed to its testing. That is because many modern IC devices perform complex functions, have a large number of inputs and outputs, and operate at high speeds. For instance, a 256 Mb memory device may have 16 data lines and 22 address lines. A simplistic approach to test such a device would be to write a known data value to each memory location, and then read from each location, and then compare the value read to the expected or written value to determine any errors. However, because of the large number of locations, each containing several bits, such a technique of testing each bit of each location is very time consuming. As a result, the field of test engineering has developed to create efficient techniques for detecting as many errors as possible while using the least number of test sequences.
A memory device may be tested using an automated semiconductor tester. FIG. 1 shows such a tester 108 having a number (N) of channels for parallel testing of a number of devices under test (DUTs) such as DUT 118. The tester 108 normally executes a test program and in response generates data and addresses on each channel which define a complex test sequence 106 engineered for testing the particular DUTs. Each channel of the tester 108 feeds a respective DUT so that a number of DUTs, corresponding to the number of channels, are tested simultaneously. A probe card (not shown) receiving all N channels delivers address and write data of the test sequence 106 to locations in N different DUTs simultaneously, while the DUTs are still part of a semiconductor wafer 116. The tester 108 then reads from those locations and performs a comparison with expected data it generates. The results of the comparison help determine whether a particular bit read from a location in a DUT is in error. The tester 108 performs the above read and write cycles many times with the same or different data patterns to verify as many locations of the DUTs as possible given time and budget constraints.
To increase throughput in terms of the number of DUTs tested per unit time, a larger tester may be built having more channels. Such a solution, however, could be prohibitively expensive. The tester is a complex and high speed machine, requiring much time and expense to modify or improve. Moreover, a single channel of a modern tester may comprise between 50 to 100 signal wires, such that increasing the number of channels between the tester and the probe card will make it physically impractical to connect all of the signal wires to the probe card. Therefore, a more efficient solution for increasing the throughput of an IC test system is needed.
Accordingly, an embodiment of the invention is directed to interface circuitry that essentially acts as a relay between the tester and a number of DUTs, where test vectors on each channel are fanned out to multiple DUTs. In general, the test vectors include stimuli, such as addresses, data values, and control signals, that are passed on to the DUTs while maintaining any timing constraints between the stimuli that were set up by the tester. The responses by the DUTs to these stimuli may then be collected by the interface circuitry and relayed back to the tester. If desired, the interface circuitry may be further enhanced with error detection capability based on the responses. For instance, the response from each DUT may be evaluated for internal consistency, by within-DUT and across-DUT comparisons, or it may be evaluated by comparison to expected responses received from the tester. The results of the comparison may then be provided back to the tester in summary or in detail form.
In a further embodiment, a system is disclosed for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the circuitry performs a first comparison of the values of two locations having corresponding addresses in different DUTs after reading from the locations, and in response generates the error values indicative of the first comparison. The circuitry further performs a second comparison of the values of two different locations in the same DUT to generate further error values indicative of the second comparison.
These as well as other features and advantages of various embodiments of the invention can be better appreciated by referring to the claims, written description, and drawings below.